Timing Driven Genetic Algorithm for Standard-cell Placement
نویسندگان
چکیده
In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. A t early generations, the search is biased toward solutions with superior tarning characteristics. As the algorithm starts converging toward generations with acceptable de lay properties, the objective is dynamically adjusted toward optimizing area and routability. Experiments with test circuits demonstrate delay performance improvement by up to 20%. Without any noticeable loss in solution quality, sizable reduction in runtime is obtained when population size as allowed to decrease an a controlled manner whenever the search hits a plateau.
منابع مشابه
Standard Cell Placement using Iterative & Constructive Heuristics for Multi-Objective Optimization
Focus in the present rests on optimization of multi-objective standard cell placement for maximizing the speed and minimizing power and interconnect wire-length with cell-width as a constraint. It incorporates fuzzy cost function rules for designing of multi-objectives to integrate the cost of above defined objectives. A significant improvement is reported when the iterative-constructive standa...
متن کاملPar-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs
In this paper, we present a parallel algorithm running on a shared memory multi-processor workstation for timing driven standard cell layout. The proposed algorithm is based on POPINS2.0 [13] and consists of three phases. First, we get an initial placement by a hierarchical timing-driven mincut placement algorithm. At the top level of partitioning hierarchy, we perform one step of bi-partitioni...
متن کاملIncremental Timing Driven Placement
Standard cell layouts may need only slight modifications to meet timing constraints. In these situations, general purpose algorithms, which consider numerous parameters of the layout, may be too time consuming or too coarse to make the changes where needed. This paper presents an incremental timing driven placement algorithm designed to “cleanup” a handful of critical paths in a previously plac...
متن کاملA Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process, and as a result several research efforts have been undertaken to parallelize this algorithm. Parallel placement is most needed for very large circuits. Since these circuits do not fi t in memory, the traditional approach has been to partition and place individual modules...
متن کاملA Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing based placement has minimized area, but with deep submicron design, minimizing wirelength delay is also needed. The algorithm discussed in this paper is the first parallel algorithm for timing driven placement. We have us...
متن کامل